Non-volatile semiconductor memory devices may be generally divided into floating gate type non-volatile semiconductor devices and charge trapping type non-volatile semiconductor devices based on the cell structure of the device. An example of a charge trapping type non-volatile semiconductor device is a silicon-oxide-nitride-oxide-semiconductor (SONOS) type non-volatile semiconductor device.
In floating gate type non-volatile semiconductor devices, a unit cell of the device typically includes a tunnel oxide layer, a floating gate, a dielectric layer and a control gate that are sequentially stacked on a substrate. Charges may be stored between the floating gate and the dielectric layer as free electrons in order to program a unit cell of the device. To erase the unit cell, the stored charges may be emitted from the floating gate and the dielectric layer. When defects are present in the tunnel oxide layer of floating gate type non-volatile semiconductor devices, charges stored between the floating gate and the dielectric layer may be dissipated from the floating gate. Accordingly, to reduce or minimize such charge loss, floating gate type non-volatile semiconductor devices may include a relatively thick tunnel oxide layer. However, as the thickness of the tunnel oxide layer is increased, the driving voltage of the device may be increased and/or the peripheral circuits may become more complicated. Thus, floating gate type non-volatile semiconductor devices that include a thick tunnel oxide layer may exhibit lower levels of integration.
A unit cell of a SONOS type non-volatile semiconductor device usually includes a tunnel insulation layer, a charge trapping layer, a blocking insulation layer and a gate electrode that are stacked on a substrate. The tunnel insulation layer and the blocking insulation layer may be formed using oxides, whereas the charge trapping layer is formed using nitride. The gate electrode may be formed using a conductive material. To program a SONOS type non-volatile semiconductor device, charges such as electrons may be stored in charge trapping sites of the charge trapping layer. The stored charges may be emitted from the charge trapping layer in order to erase the SONOS type non-volatile semiconductor device. Since the charges may be stored in charge trapping sites that have deep energy levels, the tunnel insulation layer may be relatively thin. When the tunnel insulation layer is thin, the SONOS type non-volatile semiconductor device may have a low driving voltage and simplified peripheral circuits. Thus, the SONOS type non-volatile semiconductor device may be highly integrated.
Recently, the SONOS type non-volatile semiconductor devices have been introduced that include charge trapping layers that are separated from each other by the unit cell so as to reduce or prevent lateral migration of the charges between adjacent charge trapping layers. These SONOS type non-volatile semiconductor devices may have improved threshold voltages.
Pursuant to conventional methods of manufacturing SONOS type non-volatile semiconductor devices, a tunnel insulation layer, a charge trapping layer, an etch stop layer and a mask layer are sequentially formed on a semiconductor substrate. The tunnel insulation layer and the charge trapping layer are formed using oxide and nitride, respectively. The mask layer is patterned to form a mask on the etch stop layer. The etch stop layer, the charge trapping layer and the tunnel insulation layer are partially etched using the mask so that a trench is formed through the tunnel insulation layer, the charge trapping layer and the etch stop layer. After the trench is filled with an insulation layer, the etch stop layer, the mask and an upper portion of the insulation layer are removed. Thus, an isolation layer is formed in the trench, and a tunnel insulation layer pattern and a charge trapping layer pattern are formed between adjacent isolation layers.
FIG. 1 is an electron microscopic photograph showing a trench formed in accordance with the above-described conventional method of manufacturing the SONOS type non-volatile semiconductor devices. As shown in FIG. 1, the trench may not have the desired structure because, during the etching of the charge trapping layer and the tunnel insulation layer, the etching rate of the charge trapping layer may be different from the etching rate of the tunnel oxide layer. When the trench has a poor structure, the isolation layer that is formed in the trench may include one or more voids. Further, the charge trapping layer pattern may be damaged during the etching process.